As semiconductor devices have become more highly integrated, the width of metal interconnects of semiconductor devices has also been reduced. Such reduction in the width of the interconnects may cause electro migration (EM) due to an increase in an electrical current density, thereby deteriorating the reliability of the metal interconnect. To obviate such problem, instead of aluminum, copper has been suggested as a new interconnect material for semiconductor devices. Copper has a lower specific resistance than the aluminum and ensures high interconnect reliability. However, copper cannot form a fine interconnect pattern by using a dry etching process because copper compounds have low volatility.
To solve the problem patterning with copper, a damascene process has been developed. The damascene process forms a copper interconnect of a semiconductor device by depositing an interlayer dielectric (ILD) layer on a semiconductor device, forming a trench through the ILD layer by using a photolithography process, filling the trench with copper, and performing a chemical mechanical polish (CMP) process for the copper trench. Particularly, a dual damascene process, which is broadly used for forming multi-layer metal interconnects, forms a via and a metal interconnect at the same time by using only one CMP process.
A known dual damascene process deposits a first insulating layer on a substrate having at least one predetermined structure. An etch-stop layer and a second insulating layer are sequentially deposited on the first insulating layer. A first photoresist pattern for a via hole is formed on the second insulating layer by using a photolithography process. The second insulating layer, the etch-stop layer, and the first insulating layer are dry-etched by using the first photoresist pattern as a mask. The first photoresist pattern is then removed to complete a via hole through the first insulating layer. A second photoresist pattern for a trench is formed on the resulting structure by using a photolithography process. The second insulating layer is dry-etched by using the second photoresist pattern as a mask. The second photoresist is removed to complete a trench for a metal interconnect through the second insulating layer. The via hole and the trench are filled with copper and planarized by a planarization process to form a via and a copper interconnect.
However, the copper interconnect formed by the above-described known method may be oxidized while it is exposed to the air because a dangling bond in the surface of the copper interconnect reacts with oxygen in the air. To prevent the oxidation of the copper interconnect, a barrier metal layer and a copper seed layer should sequentially be deposited on the copper interconnect within nine hours after the copper interconnect is exposed to the air.